1. Technical Field
Various embodiments of the inventive concept relate to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a vertical transistor and a method for manufacturing the same.
2. Related Art
With increase in the integration degree of semiconductor devices, a channel length of a transistor becomes reduced. The reduced channel length causes short channel effects such as Drain Induced Barrier Lowering (DIBL), a hot carrier effect and punch-through.
For resolving the concerns, solutions are suggested as reducing a length of a junction region and increasing the channel length by forming a recess in a channel region of a transistor.
However, as the integration degree increases due to the semiconductor devices with the capacity of giga bits, it becomes difficult to satisfy the desired device area of a flat structure of transistor, in which junction regions are formed at both sides of a gate electrode, in spite of the scaled down channel length. Therefore, to resolve the concern, a vertical channel transistor is suggested.
A semiconductor device having a vertical channel transistor in the related art will be described with reference to FIG. 4.
The semiconductor device in the related art includes a plurality of pillars 215 vertically extending from a semiconductor substrate 210, a gate insulating layer 230 surrounding a lower lateral surface of each pillar 215, a gate electrode 240 surrounding each pillar 115 surrounded with the gate insulating layer 230 and a spacer 250 surrounding an upper lateral surface of the pillar 215. A silicide layer 280 is formed on an upper surface of the pillar 215 and a lower electrode 290 is formed on the silicide layer 280.
With trend of shrinkage in the semiconductor device having the vertical channel transistor such as a phase-change random access memory (PCRAM), difficulty in a process is seriously increased. In the semiconductor device of 20 nm or less, ON current is reduced due to increase in a contact resistance by the shrinkage trend.
Therefore, in the recent semiconductor devices, there is a need for increasing the ON current by reducing the contact resistance.